In recent years, techniques such as those disclosed by Patent Literature 1 are proposed for implementing global shutter operation by a CMOS image sensor.
FIG. 28 illustrates the shutter operations of the CCD image sensor and the MOS image sensor. As illustrated in the diagram, the CCD image sensor performs the global shutter operation with which all of the pixels are exposed simultaneously. In contrast, the MOS image sensor generally performs the rolling shutter operation with which the pixels in the same row are exposed simultaneously. With the rolling shutter, there is a time lag between the shutter timing for the pixels in the first read-out row and the shutter timing for the pixels in the last read-out row, leading to a problem of distortion occurring in the shape of an object that moves at high speed.
In view of the foregoing, the conventional technique illustrated in FIG. 29 is disclosed (Patent Literature 1).
FIG. 29 is a block diagram which illustrates a configuration of a conventional solid-state image capturing element 200. As illustrated in FIG. 29, the solid-state image capturing element 200 includes: pixel cells 201 each of which converts a light signal into an electric signal; a pixel circuit unit 202 in which the pixel cells 201 are arranged in a matrix; a vertical scanning unit 203 which selects a vertical line (row) of the pixel circuit unit 202; a noise suppression unit 231 which suppresses noise of a pixel signal transmitted from the selected row; a memory unit 222 in which storage cells 221 for accumulating an output signal from the noise suppression unit 231 are arranged in a matrix; a vertical memory scanning unit 223 which selects a vertical line (memory row) of the memory unit 222; a horizontal selecting unit 205 which selects a signal of the selected memory row; a horizontal scanning unit 206 which sequentially selects the horizontal selecting unit 205 in a horizontal direction; and an output amplifier 212.
FIG. 30 is a circuit diagram which illustrates the configuration of the noise suppression unit 231 and the memory unit 222 illustrated in FIG. 29. The storage cell 221 provided in the memory unit 222 includes: a memory capacitor C31 which accumulates the output signal from the noise suppression unit 231; a memory write transistor M31 for writing the output signal into the memory capacitor C31; a memory amplifier A31 which amplifies the signal accumulated in the memory capacitor C31; and a memory read transistor M32 which reads an output from the memory amplifier A31.